For as long as most engineers have been writing software, memory has been a strictly local resource. Every server has its own bank of DRAM, wired directly to its own CPU sockets, and if you run out, your options are to add more DIMMs (up to a hard physical limit) or buy a bigger machine. Compute Express Link, or CXL, is the first industry-wide effort to break that assumption in a serious way, and it’s worth understanding because it changes some fairly fundamental math about how data centers get built.

What CXL actually is

CXL is an interconnect standard that runs over the same physical PCIe links already present in every modern server, but it adds a coherent protocol layer on top. “Coherent” is the key word: it means a CPU and an accelerator, or a CPU and a pool of external memory, can share access to the same memory addresses with the hardware managing consistency between them. Previously, PCIe devices could move data to and from a CPU, but they couldn’t meaningfully share a coherent memory space with it without vendor-specific tricks.

The standard is versioned, and each version added new capability. Early CXL was mostly about attaching accelerators (GPUs, smart NICs, FPGAs) with lower latency and shared memory semantics than plain PCIe allowed. Later versions introduced memory pooling and switching, which is the part that matters most for general-purpose servers.

Why memory needed unbundling

CPU core counts have grown much faster than the number of memory channels a socket can practically support. That creates a mismatch: you can pack more cores into a chip, but each core ends up with less memory bandwidth and capacity to work with unless you keep adding channels, which runs into pin count, power, and board layout limits. Meanwhile, DRAM is expensive and it’s common for a fleet of servers to have wildly uneven memory utilization: some machines starved for RAM, others sitting on capacity they’ll never touch.

The traditional fix for uneven utilization was over-provisioning every box with enough memory to handle its worst case, which is expensive at fleet scale. CXL offers a different fix: attach memory to a shared pool that multiple hosts can draw from, and let software or firmware allocate it dynamically based on actual demand rather than worst-case guesses.

Pooling and tiering

Two related ideas tend to get bundled under the CXL banner. Memory pooling is the ability for multiple servers to share a common bank of memory attached through a CXL switch, expanding or shrinking each host’s allocation without physically touching hardware. Memory tiering is the idea that not all memory needs the same latency characteristics. Hot, latency-sensitive data stays in local DRAM, while colder data can live in CXL-attached memory that’s slightly farther away (and possibly cheaper per gigabyte) but still far faster than going to storage.

This tiering model mirrors what already happened with storage a decade earlier: hot data on NVMe, warm data on cheaper SSDs, cold data on object storage. CXL brings that same tiered mindset into the memory hierarchy itself, with an extra rung below DRAM but well above disk.

The catch: latency and software awareness

None of this is free. CXL-attached memory has higher latency than memory sitting directly on a CPU’s local channels, because the request has to traverse the interconnect and possibly a switch. That’s fine for workloads with a lot of cold or infrequently touched data, and a problem for workloads that assume uniform, low-latency access to everything. This means operating systems and applications increasingly need to be tier-aware: deciding what belongs in fast local memory versus the CXL-attached pool, either automatically through OS-level hot-page tracking or explicitly through application hints.

This is the same non-uniform memory access challenge multi-socket servers have dealt with for years, just extended one hop further and across host boundaries. Kernel and hypervisor support for CXL memory tiering is still maturing, which is part of why adoption has been gradual rather than a sudden format switch.

Where this leads

CXL’s long-term trajectory points toward composable infrastructure: racks where compute, memory, and accelerators are pooled resources assembled per workload rather than fixed at the chassis level, similar in spirit to what’s already happened with compute-storage disaggregation. Memory is simply the next component to get unbundled from the physical server chassis. It won’t replace local DRAM, but it gives operators a real lever for fleet-wide memory efficiency that didn’t exist before, and it’s a good example of how a boring-sounding interconnect spec can quietly reshape data center economics.