Every time you run a program on a modern multicore system, the operating system can schedule it on any available CPU core without worrying about which memory that core can reach. That seemingly simple capability—any core accessing any memory address—is the fundamental characteristic of symmetric multiprocessing, and it shapes how we build both hardware and software.

What Makes It Symmetric

In an SMP system, all processor cores share equal, uniform access to a single pool of main memory. There’s no distinction between “core 0’s memory” and “core 7’s memory.” Every core connects to the same memory controller and address space through a shared bus or interconnect. When core 2 writes to address 0x4000, core 5 can read that same address without indirection or message passing.

This symmetry extends beyond memory. All cores see the same I/O devices, the same interrupt controllers, and the same system resources. Any core can handle any interrupt. Any core can execute any process or thread. The hardware provides no privileged or special-purpose processors; they’re architecturally identical and interchangeable from the operating system’s perspective.

The contrast is with asymmetric multiprocessing, where different processors have distinct roles or isolated memory regions, or with distributed systems where each node has genuinely local memory and remote access requires explicit network operations.

Why Operating Systems Depend On It

SMP eliminates the need for the OS to track which memory belongs to which processor. The kernel maintains a single unified page table hierarchy that all cores share. Process migration becomes trivial: moving a thread from core 1 to core 4 requires updating a scheduler data structure, not copying memory or remapping address spaces.

The shared memory model also simplifies synchronization primitives. Mutexes, semaphores, and atomic operations work because all cores can perform compare-and-swap or load-linked/store-conditional instructions on the same memory locations. Lock-free data structures depend on this: when one core atomically updates a shared pointer, every other core immediately sees the result without requiring software-level coherence protocols.

Interrupt load balancing becomes straightforward. When a network packet arrives, the interrupt controller can wake any idle core to handle it. The receiving core writes the packet data into kernel memory that any other core can then process. There’s no affinity constraint tying I/O handling to specific processors.

The Cache Coherence Cost

Of course, shared memory across multiple cores isn’t free. SMP requires cache coherence protocols—typically MESI or MOESI variants—to keep each core’s private caches consistent with each other. When core 0 writes to a cache line, the coherence protocol must invalidate or update copies held by other cores.

This coordination happens entirely in hardware, invisible to software, but it has performance implications. High-contention shared variables cause cache line ping-ponging between cores. False sharing occurs when unrelated variables occupy the same cache line, forcing unnecessary coherence traffic. Heavily parallel workloads can become bandwidth-limited by coherence protocol overhead rather than by compute capacity.

Yet the tradeoff is deliberate: hardware-managed coherence complexity in exchange for a simple, uniform programming model. Developers write concurrent code using threads and locks without manually propagating updates between processors.

NUMA: When Symmetry Breaks Down

As core counts increased, pure SMP hit scaling limits. Modern servers often use NUMA—non-uniform memory access—where each processor socket has local memory that it can access faster than remote memory attached to other sockets. Technically, all memory remains globally addressable, preserving the SMP programming model, but access latency is no longer symmetric.

NUMA is a pragmatic compromise. It retains SMP’s shared address space and uniform programming model while improving bandwidth and latency through locality. Operating systems provide NUMA-aware scheduling and memory allocation to keep threads near the data they access, but the fundamental SMP guarantee—any core can access any memory—remains intact.

Why It Still Matters

Even as architectures evolve, SMP’s core abstraction persists. Every mainstream server, desktop, and phone is built on the assumption that cores are interchangeable and memory is shared. Schedulers, runtime systems, and applications all depend on that uniform access model.

The alternative—manually partitioning memory across processors or building distributed-memory programming models into every application—would push enormous complexity onto developers. SMP keeps that complexity in hardware where it can be solved once, correctly, and invisibly. That’s why it remains the foundation of concurrent programming decades after its introduction.